The fabrication of three-dimensional structures in silicon is used extensively in the manufacture of micro-electro-mechanical (MEMS) devices. Often such structures have high aspect ratios (AR) and depths ranging from tens to hundreds of micrometers. Moreover, most of device design requires structures with different dimensions and thus different ARs to co-exist on a single microchip.
Numerous processing techniques have been applied to fabricate three-dimensional microstructures. Dry etching using a reactive gas in the plasma state is one of the more commonly employed processes for silicon etching. A time division multiplexed (TDM) plasma etching technique, which has been described by Suzuki et al. (U.S. Pat. No. 4,579,623), Kawasaki et al. (U.S. Pat. No. 4,795,529) and Laermer et al. (U.S. Pat. No. 5,501,893) is typically used for MEMs applications. The TDM etch process is typically carried out in a reactor configured with a high-density plasma source and a radio-frequency (RF) biased substrate electrode. TDM etch processes employ alternating etching and deposition steps. For example, in etching a silicon substrate, sulfur hexafluoride (SF6) is used as the etch gas and octofluorocyclobutane (C4F8) as the deposition gas. In an etch step, SF6 facilitates spontaneous and isotropic etching of silicon; in a deposition step, C4F8 facilitates protective polymer passivation onto the sidewalls as well as the bottom of etched structures. In the subsequent etching step, upon energetic and directional ion bombardment, the polymer film coated in the bottom of etched structures from the preceding deposition step will be removed to expose the silicon surface for further etching. The polymer film on the sidewall will remain, inhibiting lateral etching. The TDM processes cyclically alternate between etch and deposition process steps to enable high aspect ratio structures to be defined into a masked silicon substrate at high etch rates. FIG. 1 provides a schematic illustration for TDM etch processes.
TDM processes consist of multiple steps. A group of steps (e.g., etch and deposition) is called a cycle. Two or more “repeats” of a cycle is called a loop. As multiple cycles are sequentially executed in a loop, it is known in the art to make small changes in the step recipe parameters to enhance profile control (e.g., morphing). In the morphed case, a loop will consist of a series to two or more cycles wherein the steps within a cycle are not strictly identical cycle to cycle. The steps within a cycle may be further divided into one or more sub-steps (e.g., the etch step can be subdivided into a polymer removal sub-step and an isotropic silicon etch sub-step).
There is a well-documented aspect ratio dependent etching (ARDE) phenomenon in deep silicon etching. It has been observed that the silicon etch rate decreases as the depth or aspect ratio (defined as the feature depth divided by the feature width) increases. During the fabrication of three dimensional structures, the ARDE effect can be manifested in two ways. First, as an etch process proceeds for a feature of constant width, the feature aspect ratio increases with increasing etch time resulting in an etch rate decrease over time. Second, when features of different dimension are present on the same substrate, and etched together simultaneously, wider trenches are etched at faster rates than narrower trenches. In both cases, the etch rate decreases as aspect ratio increases. An example of ARDE is shown in the cross section of FIG. 2. In this case, trenches with widths ranging from 2.5 μm to 100 μm were located adjacent to one another and etched in one process. ARDE lag, sometimes called reactive ion etching (RIE) lag, is measured as trench depths are normalized to that of a 100 μm-wide trench, and the result is given in FIG. 3. In this case, when the 100 μm-wide trench is etched to a depth of 130 μm, a 10 μm-wide trench is only etched to a depth of 94 μm and 2.5 μm-wide trench is only etched to a depth of 62 μm.
The ARDE effect presents challenging complications to MEMS device fabrication. When structures with various lateral dimensions coexist and are etched at once, the resulting vertical dimensions are different, which may be incompatible with device design requirements. Even for a single structure, as etching progresses, the vertical etch rate is not constant, which could represent a process control issue. Indeed, RIE lag is a highly complex phenomenon and many mechanisms are proposed to explain the change in etch rate with increasing aspect ratio. In general, many factors contribute prominently to RIE lag such as: (i) ion flux loss at the bottom of the etched structure; and (ii) reactive neutral species depletions due to neutral shadowing and Knudsen transport.
In practice, MEMS device designers and device makers have to cope with the ARDE effect. One widely used method is to employ an etch stop layer. In silicon-on-insulator (SOI) and silicon-on-glass (SOG) wafers, a buried oxide layer is used to stop etching to compensate for the RIE lag. However, two disadvantages emerge when SOI or SOG wafers are used. The first disadvantage is notching at the silicon/oxide interface which is often undesirable. The second disadvantage is SOI and SOG wafers are more expensive than silicon wafers.
Alternatively, a number of groups have investigated other means to alleviate the ARDE effect. The following is an overview of these investigations.
Doh et al. report improvement of RIE lag at increased bias voltage and increased bias frequency in an electron cyclotron resonance (ECR) plasma etching system. Doh et al. teach etching silicon dioxide (SiO2) with C4F8+H2 plasma in an ECR system. The bias voltage is ranged from 100 to 300 volts, and bias frequency from 100 kHz to 1 MHz, and chamber pressure from 3.0 mTorr to 7.5 mTorr. Higher bias frequency and bias voltage result in significant reduction in RIE lag, and decreased pressure also contributes to smaller RIE lag. While Doh et al. teach in great detail the effects of plasma parameters on RIE lag, their technique uses a single step process and does not teach or suggest its use in a TDM process. Furthermore, the results of Doh et al. were achieved in etching silicon dioxide in contrast to the current invention which achieved results in etching silicon.
Lill et al. disclose RIE lag results in an experiment of etching polysilicon with an SF6 plasma in an inductively coupled plasma (ICP) system. Reduced RIE lag is reported at high pressure (up to 20 mTorr) and medium cathode temperature (i.e., 45° C.). While such a result is noteworthy, the polysilicon is etched with a single step process. In contrast, TDM processes utilize alternating deposition and etching schemes.
Tsujimoto et al. teach a method in which gas residence time is reduced to reduce RIE lag. Cl2 plasma is used to etch polysilicon in an ICP system. At lower chamber pressure, RIE lag is observed to decrease. However, the etching process with Cl2 plasma is not a TDM process, and the much slower etch rate and low mask selectivity with Cl2 plasma makes it impractical to etch three-dimensional structures with depths greater than a few tens of micrometers.
Chung et al. (U.S. Patent Application number 2003/0171000) teach ARDE reduction for TDM silicon etch processes through two methods. The first method teaches modifying the pattern geometry to equalize the load between the wide and narrow features. The second method teaches closing the auto pressure control valve to raise the process pressure in both the etch and deposition steps. Chung et al. do not teach increasing the deposition time, decreasing the etch time, increasing the polymer deposition rate, or decreasing the polymer removal rate to correct ARDE. In addition, Chung et al. do not teach or suggest the use of real time feedback on the etch depth difference to correct ARDE during the process.
Rickard et al. (SPIE Conference “Microelectroinic & MEMs Technologies, Edinburgh (UK), May 2001) performed a series of designed experiments to reduce ARDE using a TDM process. During their experiments they found ARDE was minimized through shorter etch times, low pressures, low platen (RF bias) powers, and increased deposition times. Rickard et al. do not disclose a method to measure the extent of lag in the process in real time. Furthermore, Rickard et al. do not disclose the use of closed loop adaptive recipe control to minimize ARDE during the TDM process.
Lill et al. (U.S. Pat. No. 6,632,321) teach the use of interferometry for real time etch rate control. The interferometer used by Lill et al. is based on an ultra-violet (UV) light source while the current invention uses a laser source. Lill et al. teach the use of a single beam to monitor the cyclical change in intensity to determine the etch rate. Whereas, the current inventors employ multiple beams to directly measure the interference as a phase difference between beams to determine the difference in their etch depth which measures the etch rate. Lill et al. teach light reflection from the surface for monitoring the etch rate, but do not teach direct measurement of at least two different feature widths for real time etch depth control. In addition, Lill et al. teach the control method to maintain a constant etch rate while the current invention does not monitor etch rate, but rather controls the process to control the etch depth difference between at least two different size features. Furthermore, Lill et al. do not contemplate applying real time control to a time division multiplex process. As a result Lill et al. do not teach the reduction of etch step time, increased polymer deposition time, reduced polymer removal rate or increased polymer deposition rate as solutions to ARDE in TDM silicon etch processes.
Ayon et al. (Journal of Electrochem. Soc., 146(1) 339-349 (1999)) teach the minimization of ARDE for TDM processes through the use of high (140 sccm) SF6 flow rates. Ayon et al. report that in the regime where ARDE was minimized that the floor of the feature profiles varied from convex to concave across the feature dimensions. This effect is undesirable. Ayon et al. do not contemplate real time measurement and control of the process to minimize ARDE.
Laermer et al. (U.S. Pat. No. 6,720,268) teach the use of optical emission spectroscopy during the process to determine when the polymer clears during a TDM process. Laermer et al. do not teach the use of a twin beam interferometer for real-time process feedback. In addition, Laermer et al. do not teach the use of real time measurement of two features simultaneously to reduce ARDE.
Hopkins et al. (U.S. Pat. No. 6,187,685) discuss the mechanisms that lead to ARDE in TDM processes. Specifically, the mechanisms are as follows: more deposition present in wide trenches as compared to narrow trenches (presumably due to transport limitations), resulting in more polymer to be removed in the wider (lower aspect ratio) feature than in narrow features, and that the silicon etch rate is higher in wider (lower aspect ratio) features, so that the net effect of the etch and passivation (removal and deposition) is to equalize the etch rates of the narrow and wide features. Hopkins et al. teach that the RIE lag compensation effect can be achieved through a number of ways which allow judicious balance of the etch and deposition conditions to achieve the same effect. Hopkins et al. teach that pulsed RF bias also exhibits ARDE reduction in TDM silicon etch processes. Hopkins et al. do not contemplate the use of real time metrology to monitor or modify the process.
Therefore, there is a need for reducing the ARDE effect in TDM processes.
Nothing in the prior art provides the benefits attendant with the present invention.
Therefore, it is an object of the present invention to provide an improvement which overcomes the inadequacies of the prior art devices and which is a significant contribution to the advancement of the semiconductor processing art.
Another object of the present invention is to provide a method for reducing aspect ratio dependent etching in a plasma etching process, the method comprising: placing a substrate in a vacuum chamber; depositing a passivation layer on said substrate by means of a plasma; removing at least a portion of said passivation layer by means of a plasma; etching a material from said substrate by means of a plasma; performing a process loop of repeating the deposition step, the removal step, and the etch step; monitoring different sized features on said substrate over time; controlling the process loop step based on said monitoring step; and removing the substrate from the vacuum chamber.
Yet another object of the present invention is to provide a method for reducing aspect ratio dependent etching in a plasma etching process, the method comprising: placing a substrate in a vacuum chamber; depositing a polymer on said substrate by means of a plasma; removing at least a portion of said polymer by means of a plasma; etching a material from said substrate by means of a plasma; performing a process loop of repeating the deposition step, the removal step, and the etch step; adjusting a process parameter in at least one step to achieve equivalent etch depths of at least two different sized features; and removing the substrate from the vacuum chamber.
Still yet another object of the present invention is to provide an apparatus for reducing aspect ratio dependent etching during plasma etching of a substrate comprising: a vacuum chamber; at least one gas supply source for supplying at least one process gas into said vacuum chamber; an exhaust in communication with said vacuum chamber; a lower electrode positioned within said vacuum chamber; a substrate holder connected to said lower electrode; a plasma source for generating a plasma within said vacuum chamber; a process controller for alternately depositing a passivation layer on the substrate by means of a plasma, removing at least a portion of the deposited passivation layer by means of a plasma, and etching a material from the substrate by means of a plasma; and a differential interferometer coupled to said process controller, said differential interferometer generating a signal indicative of a difference in depth between at least two different size features, and said process controller varying at least one process parameter in response to the signal generated by said differential interferometer.
The foregoing has outlined some of the pertinent objects of the present invention. These objects should be construed to be merely illustrative of some of the more prominent features and applications of the intended invention. Many other beneficial results can be attained by applying the disclosed invention in a different manner or modifying the invention within the scope of the disclosure. Accordingly, other objects and a fuller understanding of the invention may be had by referring to the summary of the invention and the detailed description of the preferred embodiment in addition to the scope of the invention defined by the claims taken in conjunction with the accompanying drawings.